1. Field of the Invention
The present invention relates to electronic packaging and methods of fabricating same. More particularly, the present invention relates to semiconductor chip packaging using a multilayer thin film for chip attachment to a substrate.
2. Background and Related Art
Ever increasing industry demand for smaller and smaller electronic packages with low profile, higher area density and increasing number of input/output connections (I/Os) has led to increasing demand for the Chip Scale Package (CSP). Use of such packages may be found in small portable products, such as cellular phones, pagers, and the like. However, it is known that CSPs have somewhat limited applications because of the limited number of I/Os due to solder interconnect reliability constraints. As feature sizes of the semiconductor chip packages decrease, as in the case of CSPs, and the I/O connection count increases, so too will the number of chips packaged in a given area. This will increase the heat dissipated by each of the chips which will, in turn, increase the thermal mismatch stresses between chip and substrate, the latter of which will decrease the interconnect reliability of the package. Various efforts have been made in the prior art to address the thermal mismatch problem. In addition, various efforts have been made to improve interconnect reliability and reduce cost by, for example, fabricating CSPs at the wafer level. However, these efforts have not been totally successful and have involved relatively complex and costly assemblies with limited capability.
In view of the limitations of prior art chip packaging mentioned hereinabove, there continues a need for a relatively simple, low profile, high density, chip packaging approach which has high interconnect reliability and high I/O connection count, and which may use relatively low-cost wafer scale processing.